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CT T OD U M EN E PR PLACE 143 ET OL RE 4-7 O BS E NDE D 1-72 or 32 M M IL E CO E RS NO R -888-INT 1 Call
TM
CA3098
January 1999 File Number 896.5
Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector
The CA3098 Programmable Schmitt Trigger is a monolithic silicon integrated circuit designed to control high operating current loads such as thyristors, lamps, relays, etc. The CA3098 can be operated with either a single power supply with maximum operating voltage of 16V, or a dual power supply with maximum operating voltage of 8V. It can directly control currents up to 150mA and operates with microwatt standby power dissipation when the current to be controlled is less than 30mA. The CA3098 contains the following major circuit function features (see Block Diagram): 1. Differential amplifiers and summer: the circuit uses two differential amplifiers, one to compare the input voltage with the "high" reference, and the other to compare the input with the "low" reference. The resultant output of the differential amplifiers actuates a summer circuit which delivers a trigger that initiates a change in state of a flipflop. 2. Flip-flop: the flip-flop functions as a bistable "memory" element that changes state in response to each trigger command. 3. Driver and output stages: these stages permit the circuit to "sink" maximum peak load currents up to 150mA at terminal 3. 4. Programmable operating current: the circuit incorporates access at terminal 2 to permit programming the desired quiescent operating current and performance parameters.
Features
* Programmable Operating Current * Micropower Standby Dissipation * Direct Control of Currents Up to . . . . . . . . . . . . . . . 150mA * Low Input On/Off Current of Less Than 1nA for Programmable Bias Current of 1A * Built-in Hysteresis . . . . . . . . . . . . . . . . . . . . . 20mV (Max)
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Applications
* Control of Relays, Heaters, LEDs, Lamps, Photosensitive Devices, Thyristors, Solenoids, etc. * Signal Reconditioning * Phase and Frequency Modulators * On/Off Motor Switching * Schmitt Triggers, Level Detectors * Time Delays * Overvoltage, Overcurrent, Overtemperature Protection * Battery-Operated Equipment * Square and Triangular-Wave Generators
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Part Number Information
PART NUMBER CA3098E TEMP RANGE ( oC) -55 to 125 PACKAGE 8 Ld PDIP PKG. NO. E8.3
t ent, Pinout
CA3098 (PDIP) TOP VIEW
le low l ut, ure itt ilt is, put
LOW REF. I BIAS OUT V-
1 2 3 4
8 +IN 7 HIGH REF. 6 V+ 5 CURRENT CONTROL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved
CA3098 Block Diagram
2 PROGRAMMABLE BIAS CURRENT INPUT (IBIAS) 6 V+ OUTPUT CURRENT CONTROL 5 DIFF. AMP "SINK OUTPUT" SUMMER FLIP-FLOP (MEMORY) DRIVER OUTPUT 3
"HIGH" REF. (HR) 7 SIGNAL INPUT 8
"LOW" REF. (LR) 1
DIFF. AMP COMPARATOR
SUBSTRATE
4
V-
Schematic Diagram
6 Q8 Q10 Q22 Q23 Q20 Q24 OUTPUT CURRENT CONTROL 5 Q41 Q26 SIGNAL INPUT 8 Q5 Q30 Q31 Q16 Q33 Q43 Q44 Q45 Q27 Q28 Q29 Q42 R14 500 "SINK" OUTPUT 3 Q46 Q39 V+
Q6 "HIGH" REF. (HR) 7
Q7
Q9
Q11 Q1 Q2 Q3 Q4
Q25 Q40
Q32
R3 50K
"LOW" REF. (LR) 1
Q14 Q12 Q15 Q34 Q19 Q17 Q18 Q37 2 PROGRAMMABLE BIAS CURRENT INPUT (IBIAS)
V4
Q35
Q36
Q38
2
CA3098
Absolute Maximum Ratings
Supply Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . .16V Voltage Between High Reference or Sink Output and V-. . . . . . .16V Differential Input Voltage Between Terminals 8 and 1 . . . . . . . . .10V and Terminals 7 and 8 Load Current (Terminal 3) (Duty Cycle 25%) . . . . . . . . . . . . 150mA Input Current to Voltage Regulator (Terminal 5) . . . . . . . . . . . 25mA Programmable Bias Current (Terminal 2) . . . . . . . . . . . . . . . . . 1mA Output Current Control (Terminal 5). . . . . . . . . . . . . . . . . . . . . 15mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125oC/W Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package). . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range +IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ HIGH REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V- +2.0V) to V+ LOW REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) to (V+ -2.0V)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified CA3098 SYMBOL VIO(LR) VIO(HR) TEST CONDITIONS VLR = GND, V HR = V+ to (V- +2V), IBIAS = 100A VHR = GND, V LR = V- to (V+ -2V), IBIAS = 100A -55oC to 125oC -55oC to 125oC VIO(HRLR)
PARAMETER Input Offset Voltage "Low" Reference (Figures 2, 5) "High Reference (Figures 2, 6) Temperature Coefficient "Low" Reference (Figure 7) "High" Reference (Figure 8) Minimum Hysteresis Voltage (Figure 9) Temperature Coefficient (Figure 10) Output Saturation Voltage (Figures 11, 12) Total Supply Current "ON" (Figures 3, 13, 14) "OFF" (Figures 3, 13, 14) Input Bias Current (Figures 3, 15) IB(PNP) IB(NPN) Output Leakage Current Switching Times (Figures 4, 16-27) Delay Time Fall Time Rise Time Storage Time Output Current (Note 2)
MIN -15 -10
TYP -3 -1
MAX 6 10
UNITS mV mV
-
4.5 8.2 3 6.7 0.72
20 1.2
V/oC V/oC mV V/oC V
VREG = 0V (Note 1), V+ = 4V, V- = -4V, IBIAS = 1A -55oC to 125oC
VCE(SAT) VI = 5V, VREG = 6V (Note 1), V+ = 12V, IBIAS = 100A ITOTAL VI = 6V, VREG > 6V (Note 1), V+ = 16V, IBIAS = 100A VI = 10V, VREG < 10V (Note 1), V+ = 16V, IBIAS = 100A IIB VI = 16V, VREG < 16V (Note 1), V+ = 16V, IBIAS = 100A VI = 6V, VREG > 6V (Note 1), V+ = 16V, IBIAS = 100A ICE(OFF) tD tF tR tS IO Current from Terminal 3 when Q46 is "OFF" IBIAS = 100A, V+ = 5V, V REG = 2.5V (Note 1)
500 400
710 560
800 750
A A
100
42 28 900 30 2000 6.5 -
100 100 10 -
nA nA A ns ns ns s mA
NOTES: 1. For definition of VREG see Figure 3. 2. Continuous (DC) output current must be limited to 40mA. For 100mA output current, the duty cycle must be 40%. 3. JA is measured with the component mounted on an evaluation PC board in free air.
3
CA3098 General Description of Circuit Operation
When the signal input voltage of the CA3098 is equal to or less than the "low" reference voltage (LR), current flows from an external power supply through a load connected to Terminal 3 ("sink" output). This condition is maintained until the signal input voltage rises to or exceeds the "high" reference voltage (HR), thereby effecting a change in the state of the flip-flop (memory) such that the output stage interrupts current flow in the external load. This condition, in turn, is maintained until such time as the signal again becomes equal to or less than the "low" reference voltage. The CA3098 comparator is unique in that it contains circuit provisions to permit programmability. This feature provides flexibility to the designer to optimize quiescent power consumption, input circuit characteristics, hysteresis, and additionally permits independent control of the comparator, namely, pulsing, strobing, keying, squelching, etc. Programmability is accomplished by means of the bias current (IBIAS) supplied to Terminal 2. An auxiliary means of controlling the magnitude of load current flow at Terminal 3 is provided by "sinking" current into Terminal 5. Figure 1 highlights the operation of the CA3098 when connected as a simple hysteresis switch (Schmitt trigger).
120k RB 2 "HIGH" REF. = 8V 7 INPUT SIGNAL EIN 8 1 "LOW" REF. = 4V 4 CA3098 6 5 3 EO V+ = 12VDC IO
RL
SEQUENCE 1 2 3 2 1
INPUT SIGNAL LEVEL 4 EIN > 0 8 EIN > 4 EIN > 8 8 EIN > 4 4 EIN > 0
OUTPUT VOLTAGE (V) (TERMINAL 3) 0 0 12 12 0
FIGURE 1. BASIC HYSTERESIS SWITCH (SCHMITT TRIGGER) AND RESULTANT OUTPUT STATES
Metallization Mask Layout
0 61 60 50 10 20 30 40 50 58
40
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
66 (1.676)
30
20
The layout represents a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions.
10
0 63 (1.600)
4
CA3098 Test Circuits
+6V IBIAS IBIAS V+ ITOTAL
1.5k 2 6 8 7 1 VI VHR VLR 4 VI CA3098 5 3 VO mA 8 7 1 150 IIB 2
mA
1.1k 110
6 5 CA3098 3
4 VREG
-6V
FIGURE 2. INPUT OFFSET VOLTAGE TEST CIRCUIT
FIGURE 3. TOTAL SUPPLY CURRENT, AND INPUT BIAS CURRENT TEST CIRCUIT
V+ IBIAS
450 2 6 VI 8 7 1 4 VREG CA3098 5 45
VI
VO 3 VO tD tS tF tR
FIGURE 4. SWITCHING TIME TEST CIRCUIT
5
CA3098 Typical Performance Curves
TA = 25 oC, V+ = +12V, VHR = 6V, VLR = 6V -4 VIO (LR) = VI - VLR HIGH REF. INPUT OFFSET VOLTAGE (mV) LOW REF. INPUT OFFSET VOLTAGE (mV) -5 4 TA = 25 oC, V+ = +12V, VHR = 6V, VLR = 0V VIO (HR) = VI - VHR
3
-3
2
-2
-1
1
0
1
10 100 PROGRAMMING BIAS CURRENT (A)
1000
0
1
10 100 PROGRAMMING BIAS CURRENT (A)
1000
FIGURE 5. INPUT OFFSET VOLTAGE ("LOW" REFERENCE) vs PROGRAMMING BIAS CURRENT
FIGURE 6. INPUT OFFSET VOLTAGE ("HIGH" REFERENCE) vs PROGRAMMING BIAS CURRENT
VIO (LR) = VI - VLR
HIGH REF. INPUT OFFSET VOLTAGE (mV)
LOW REF. INPUT OFFSET VOLTAGE (mV)
3
IBIAS = 100A VIO (HR) = VI - VHR
-3.5 -3.0 -2.5 -2.0 -1.5 -75
2
1
-50
-25
0 25 50 75 TEMPERATURE (oC)
100
125
0 -75
-50
-25
0 25 50 75 TEMPERATURE (oC)
100
125
FIGURE 7. INPUT OFFSET VOLTAGE ("LOW" REFERENCE) vs AMBIENT TEMPERATURE
FIGURE 8. INPUT OFFFSET VOLTAGE ("HIGH" REFERENCE) vs AMBIENT TEMPERATURE
4 MIN. HYSTERESIS VOLTAGE (mV)
MIN. HYSTERESIS VOLTAGE (mV) 1000
TA = 25oC, V+ = +12V, VHR = 6V, VLR = 6V
4
3
3
2
1
2
0
1
10 100 PROGRAMMING BIAS CURRENT (A)
1 -100
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 9. MINIMUM HYSTERESIS VOLTAGE vs PROGRAMMING BIAS CURRENT
FIGURE 10. MINIMUM HYSTERESIS VOLTAGE vs AMBIENT TEMPERATURE
6
CA3098 Typical Performance Curves
1.4 OUTPUT SATURATION VOLTAGE (V) 1.2 1.0 0.8 0.6 0.4 0.2 0 10 TA = 25 oC, IBIAS = 100A V+ = 12V
(Continued)
IBIAS = 100A V+ = 10V
OUTPUT SATURATION VOLTAGE (V)
1.0 0.9 0.8 0.7 0.6 0.5 -100
100 OUTPUT SINK CURRENT (mA)
1000
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 11. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT
10,000 TOTAL SUPPLY CURRENT (A)
FIGURE 12. OUTPUT SATURATION VOLTAGE vs AMBIENT TEMPERATURE
TA = 25 oC, V+ = 12V VREG = 6V (NOTE) TOTAL SUPPLY CURRENT (A)
800 IBIAS = 100A 700 600 500 400 300 200
1,000
100
10
1
0.1 1 10 100 PROGRAMMING BIAS CURRENT (A) 1000 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC)
NOTE: See Figure 3 for definition of VREG FIGURE 13. TOTAL SUPPLY CURRENT vs PROGRAMMING BIAS CURRENT
FIGURE 14. TOTAL SUPPLY CURRENT vs AMBIENT TEMPERATURE
100 INPUT BIAS CURRENT (nA)
TA = 25 oC, V+ = 12V VREG = 6V (NOTE)
1050 TA = 25oC IBIAS = 100A VLR = VHR = VREG = V+/2
1000 IIB (p-n-p) IIB (n-p-n) 1 DELAY TIME (ns) 1000 10
950
900
850 0.1 1 10 100 PROGRAMMING BIAS CURRENT (A) 800 5 10 POSITIVE SUPPLY VOLTAGE (V) 15
NOTE: See Figure 3 for definition of VREG FIGURE 15. INPUT BIAS CURRENT vs PROGRAMMING BIAS CURRENT
FIGURE 16. DELAY TIME vs SUPPLY VOLTAGE
7
CA3098 Typical Performance Curves
TA = 25 oC OUTPUT FALL TIME (ns) IBIAS = 100A VLR = VHR = VREG = V+/2 STORAGE TIME (ns) 7000 40
(Continued)
TA = 25 oC IBIAS = 100A VLR = VHR = VREG = V+/2
35
30
6500 5 10 POSITIVE SUPPLY VOLTAGE (V) 15 5 10 POSITIVE SUPPLY VOLTAGE (V) 15
FIGURE 17. STORAGE TIME vs SUPPLY VOLTAGE
FIGURE 18. OUTPUT FALL TIME vs SUPPLY VOLTAGE
TA = 25 oC IBIAS = 100A OUTPUT RISE TIME (ns) 4000 VLR = VHR = VREG = V+/2 OUTPUT RISE TIME (ns)
2600 2500 2400 2300 2200 2100 2000 1900 1800 SUPPLY VOLTAGE = 5V IBIAS = 100A VLR = VHR = VREG = 2.5V
3000
2000
5
10 POSITIVE SUPPLY VOLTAGE (V)
15
1700
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 19. OUTPUT RISE TIME vs SUPPLY VOLTAGE
FIGURE 20. OUTPUT RISE TIME vs AMBIENT TEMPERATURE
45 SUPPLY VOLTAGE = 5V IBIAS = 100A OUTPUT FALL TIME (ns) 40 VLR = VHR = VREG = 2.5V STORAGE TIME (ns)
9000 SUPPLY VOLTAGE = 5V IBIAS = 100A VLR = VHR = VREG = 2.5V
8000
7000
35
6000
30
5000
25 -40 -20 0 20 40 60 80 TEMPERATURE (oC)
4000 -40
-20
0
20
40
60
80
100
TEMPERATURE (oC)
FIGURE 21. OUTPUT FALL TIME vs AMBIENT TEMPERATURE
FIGURE 22. STORAGE TIME vs AMBIENT TEMPERATURE
8
CA3098 Typical Performance Curves
1100 SUPPLY VOLTAGE = 5V IBIAS = 100A VLR = VHR = VREG = 2.5V DELAY TIME (ns)
(Continued)
1100 1000 900 800 700 600 500 SUPPLY VOLTAGE = 5V TA = 25oC, VLR = VHR = VREG = 2.5V
1000 DELAY TIME (ns)
900
800
700
600 -40
-20
0
20
40
60
80
100
400 0 500 PROGRAMMING BIAS CURRENT (A) 1000
TEMPERATURE (oC)
FIGURE 23. DELAY TIME vs AMBIENT TEMPERATURE
FIGURE 24. DELAY TIME vs PROGRAMMING BIAS CURRENT
12000 11000 10000 STORAGE TIME (ns) 9000 8000 7000 6000 5000 4000 3000 0 500 PROGRAMMING BIAS CURRENT (A) 1000 SUPPLY VOLTAGE = 5V TA = 25 oC VLR = VHR = VREG = 2.5V OUTPUT FALL TIME (ns)
60 SUPPLY VOLTAGE = 5V TA = 25 oC VLR = VHR = VREG = 2.5V
50
40
30
20 10 0 0 500 PROGRAMMING BIAS CURRENT (A) 1000
FIGURE 25. STORAGE TIME vs PROGRAMMING BIAS CURRENT
FIGURE 26. OUTPUT FALL TIME vs PROGRAMMING BIAS CURRENT
3000 SUPPLY VOLTAGE = 5V TA = 25oC, VLR = VHR = VREG = 2.5V OUTPTUT RISE TIME (ns) 2500
2000
1500
1000 0 500 PROGRAMMING BIAS CURRENT (A) 1000
FIGURE 27. OUTPUT RISE TIME vs PROGRAMMING BIAS CURRENT
9
CA3098 Typical Applications
+6V +6V
= RC x ln2
C 7
1N914 6 5
12k RL 1.2k IL 3
R
10k 12k 7 RL 1.2k 5 CA3098 3 2 4 1 1N914 60k IL
= RC x ln2
10k
6
CA3098 8 R 4 1 2 60k
8 10k C 10k
FIGURE 28. TIME DELAY CIRCUIT: TERMINAL 3 "SINKS" AFTER SECONDS
+6V
FIGURE 29. TIME DELAY CIRCUIT: "SINK" CURRENT INTERRUPTED AFTER SECONDS
10k 6 V1 7 SINE WAVE INPUT 8 1 V2 4 CA3098 2 60k 3 SQUARE WAVE OUTPUT 5 1k
-6V
FIGURE 30. SINE WAVE TO SQUARE WAVE CONVERTER WITH DUTY CYCLE ADJUSTMENT (V 1 AND V2)
2k TH1 UPPER THRESHOLD ADJUST 10k TH2 LOWER THRESHOLD ADJUST 10k 5k
120k 10k 2 6 7 8 1 4 10k T2301B MT2 CA3098 5 1k 3 G MT1 120VAC 60Hz TH2 TH1 2 1 3 WATER LEVEL TANK
NOTES: 1. Motor pump is "ON" when water level rises above thermistor TH2. 2. Motor pump remains "ON" until water level falls below thermistor TH1. 3. Thermistors, operate in self heating mode. FIGURE 31B. WATER LEVEL DIAGRAM FOR CIRCUIT
PUMP MOTOR -6V (+)
FIGURE 31A. WATER LEVEL CONTROL CIRCUIT
FIGURE 31. WATER LEVEL CONTROL APPLICATION
10
CA3098 Typical Applications
(Continued)
+6V
1M
1k
C1 7 1.1M 8 TRIGGER INPUT R4 100k R3 100k 120VAC 60Hz R1 100k SENSOR (e.g., 100k) R2 100k 8 7 1 4 CA3098 2 6 5 3 TRIAC MT2 2.5V 1k G MT1 -6V 0V 1 1k 4 60k CA3098 2 3 6 5
LAMP
DESIRED tON (ms) 15 150 300
VALUE OF C 1 (F) 0.01 0.1 0.2
LOAD
V-
FIGURE 32. OFF/ON CONTROL OF TRIAC WITH PROGRAMMABLE HYSTERESIS
FIGURE 33. ONE SHOT MULTIVIBRATOR
11
CA3098 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE -CSEATING PLANE D1 B1 B D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
eA eC
C
e
0.010 (0.25) M C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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